.. and vector generation.. Responsibilities Implementing DFT architecture features in the design. SCAN insertion, scan DRC analysis and debug. Achieving high SCAN coverage and low DPPM. ATPG vector generation and ATE BringUp. JTAG implementation and verification. MBIST and JTAG implementation and verification .. read more
Work Location:
Remote
Experience:
10 + Years
Please share updated profile to sugantha.krishnan@acldigital.com
JD Appended Below:
Candidate should have been a PM for 4-5 years minimum with direct hands on experience implementing Celergo. Must have knowledge and experience in requirements gathering, testing, interface design, production readiness, and strong payroll skills. Candidate must have strong attention to detail and be able to work with a diverse set of client personalities to define work deliverables and manage their execution to meet project schedules. This is a role that will require the ability to multitask.
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