.. chip & block level. Knowledge on DFT simulations and debugging. Knowledge on Test mode timing constraint development and analysis is a plus. Understanding of test compression and ATE debug is a plus. Having strong scripting abilities is a plus. Contact: Uday Mulya Technologies **@yahoo.com "Mining The .. read more
Aerostructure/Nacelles/Catia/MBD
Exp :
3 to 12 years
- Experience with CATIA V5
- Good to have Catia CPD design knowledge.
- Good in Microsoft Word and good knowledge of Microsoft Excel and PowerPoint.
- Aerospace structures design knowledge.
- Fair understanding of Manufacturing requirements
- Knowledge of Nacelle product and structure.
- Knowledge of aerospace structural metallic and composite design.
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