RTL Engineer and Design Verification engineer

  • kurnool

Opportunity With Tessolve Semiconductor- Bangalore

Hi All, we are hiring RTL design engineer and design verification engineer for Bangalore location. Exp: 8+ yr exp Skills: RTL ASIC, CDC, Lint, Synthesis, Spyglass .

Design verification engineer : Exp: 3 to 20 yrs Location : PAN INDIA • IP verification Using SV/UVM • SOC Verification using C/SV • Third Party VIP Integration • Interconnect Protocols: AHB, AXI, APB • SOC Interfaces: GPIO, SPI, I2C, UART (3+) • High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+) • Memory Interfaces: DDR or HBM I/O (10+) • Coverage Closure: Code, Functional and Toggle • Tools: Synopsys VCS or Cadence Incsive • Technical Documentation: Testbench Specification, Test Plan Specification • Foundry Porting Experience: Technology Library Conversion Related Changes Verification

Interested candidates, Kindly share updated cv to gayatri.kushe@tessolve.com or connect on 6361542656

Regards, Gayatri Kushe (6361542656)

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