Design Verification Engineer

  • Bengaluru
  • Acl Digital

Job Location: Bangalore/Hyderabad. Exp.-4+yrs Notice Period less than 30days.

System Verilog based UVM Functional verification, System C/C++ based functional verification. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in DDR, PCIE, CXL, Ethernet, USB- High speed, AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.

Regards, Sneha ACL Digital