.. Job description is as below: Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII, Block level Physical Signoff, Block level Timing Signoff and ECO generation. Block level Power signoff. Good skill on Automation (Perl/Tcl/Awk/Python) Able to provide technical guidance to Junior .. read more
Wafer space - An ACL Digital Company is hiring Analog/Mixed Signal layout Engineers
Experience : 4+ Years Job Location : Bengaluru,India Note : Must to available to join within 4-6 Weeks of time
Job Description
Bachelor's or Master's Degree with
4-12 years
of Analog Layout experience Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following area is preferable : Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc. Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc). Experiences in advanced technology node under 32nm/28nm/16nm/14nm/7nm.
5nm/3nm/2nm is preferable . Experience with EMIR analysis, ESD, antenna and related layout solutions. Good communication skills and willingness to work with global team. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment. Programming skills, automation and circuit Design background is a plus
Benefits
Opportunity to Work with Top Semiconductor product companies Quality of work ( Working on latest technologies in VLSI ) Competitive salary Long term Career Growth Professional development opportunities. Collaborative and innovative work environment.
Email : deepak.sawarmal@acldigital.com
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